diff --git a/audit/internal/platform/pcie_link_check.go b/audit/internal/platform/pcie_link_check.go
index 262dc15..e4add98 100644
--- a/audit/internal/platform/pcie_link_check.go
+++ b/audit/internal/platform/pcie_link_check.go
@@ -169,6 +169,12 @@ func retrainAndSamplePCIeDevice(ctx context.Context, verboseLog, bdf string, log
 			f.PortMaxWidth = f.MaxWidth
 			f.MaxSpeed = minPCIeLinkSpeed(f.MaxSpeed, peerSpeed)
 			f.MaxWidth = minPositiveInt(f.MaxWidth, peerWidth)
+			// The degradation verdict below compares against maxSpeed, so
+			// it has to track the peer-capped target too — otherwise a
+			// bridge whose port out-specs its downstream device (e.g. a
+			// Gen5 root port feeding a Gen4 HBA) is flagged DEGRADED even
+			// though the link is at the fastest rate the pair supports.
+			maxSpeed = f.MaxSpeed
 		}
 	}