package inspur

import (
	"strings"
	"testing"

	"git.mchus.pro/mchus/logpile/internal/models"
)

const cpuMemComponentLog = `RESTful version info:
[]
RESTful CPU info:
{ "processors": [ { "proc_id": 0, "PROC_ID": "A6-06-06-00-FF-FB-EB-BF", "InstructionSet": "x86-64", "Manufacturer": "Intel(R) Corporation", "MaxSpeedMHz": 3100, "configStatus": 1, "proc_name": "Intel(R) Xeon(R) Gold 6330 CPU @ 2.00GHz", "proc_status": 1, "proc_speed": 2000, "proc_core_count": 28, "proc_used_core_count": 28, "proc_thread_count": 56, "proc_tdp": 205, "proc_l1cache_size": 80, "proc_l2cache_size": 1280, "proc_l3cache_size": 43008, "micro_code": "0x0D000410", "ppin": "47149E2253E81688", "status": "OK" }, { "proc_id": 1, "PROC_ID": "A6-06-06-00-FF-FB-EB-BF", "InstructionSet": "x86-64", "Manufacturer": "Intel(R) Corporation", "MaxSpeedMHz": 3100, "configStatus": 1, "proc_name": "Intel(R) Xeon(R) Gold 6330 CPU @ 2.00GHz", "proc_status": 1, "proc_speed": 2000, "proc_core_count": 28, "proc_thread_count": 56, "proc_tdp": 205, "proc_l1cache_size": 80, "proc_l2cache_size": 1280, "proc_l3cache_size": 43008, "micro_code": "0x0D000410", "ppin": "475AC1221D41F557", "status": "OK" } ] }
RESTful Memory info:
{ "mem_modules": [ { "mem_mod_id": 0, "config_status": 1, "mem_mod_slot": "CPU0_C0D0", "mem_mod_status": 1, "mem_mod_size": 32, "mem_mod_type": "DDR4", "mem_mod_technology": "Synchronous", "mem_mod_frequency": 3200, "mem_mod_current_frequency": 2933, "mem_mod_vendor": "Samsung", "mem_mod_part_num": "M393A4K40EB3-CWE", "mem_mod_serial_num": "S1440202433526FC12", "mem_mod_ranks": 2, "status": "OK" }, { "mem_mod_id": 16, "config_status": 1, "mem_mod_slot": "CPU1_C0D0", "mem_mod_status": 1, "mem_mod_size": 0, "mem_mod_type": "DDR4", "mem_mod_technology": "Synchronous", "mem_mod_frequency": 3200, "mem_mod_current_frequency": 2933, "mem_mod_vendor": "Samsung", "mem_mod_part_num": "M393A4K40EB3-CWE", "mem_mod_serial_num": "K0UX000401205D2037", "mem_mod_ranks": 2, "status": "OK" } ], "total_memory_count": 2, "present_memory_count": 2, "mem_total_mem_size": 32 }
RESTful HDD info:
[]
RESTful PSU info:
{ "power_supplies": [] }
RESTful Network Adapter info:
{ "sys_adapters": [] }
RESTful fan info:
{ "fans": [] }
RESTful diskbackplane info:
[]
BMC done
`

func TestParseCPUInfo_FromComponentLog(t *testing.T) {
	hw := &models.HardwareConfig{}
	ParseComponentLog([]byte(cpuMemComponentLog), hw)

	if len(hw.CPUs) != 2 {
		t.Fatalf("expected 2 CPUs, got %d", len(hw.CPUs))
	}
	if !strings.Contains(hw.CPUs[0].Model, "Gold 6330") {
		t.Errorf("unexpected CPU model: %s", hw.CPUs[0].Model)
	}
	if hw.CPUs[0].Cores != 28 {
		t.Errorf("expected 28 cores, got %d", hw.CPUs[0].Cores)
	}
	if hw.CPUs[0].PPIN != "47149E2253E81688" {
		t.Errorf("unexpected PPIN: %s", hw.CPUs[0].PPIN)
	}
	if hw.CPUs[1].PPIN != "475AC1221D41F557" {
		t.Errorf("unexpected CPU1 PPIN: %s", hw.CPUs[1].PPIN)
	}
}

func TestParseMemoryInfo_PresentWithZeroSize(t *testing.T) {
	hw := &models.HardwareConfig{}
	ParseComponentLog([]byte(cpuMemComponentLog), hw)

	presentCount := 0
	for _, m := range hw.Memory {
		if m.Present {
			presentCount++
		}
	}
	if presentCount != 2 {
		t.Errorf("expected 2 present DIMMs, got %d", presentCount)
	}

	// Find CPU1_C0D0 (size=0 but serial present)
	found := false
	for _, m := range hw.Memory {
		if m.Slot == "CPU1_C0D0" {
			found = true
			if !m.Present {
				t.Error("CPU1_C0D0 should be Present=true despite size=0")
			}
			if m.SerialNumber != "K0UX000401205D2037" {
				t.Errorf("wrong serial: %s", m.SerialNumber)
			}
		}
	}
	if !found {
		t.Error("CPU1_C0D0 not found in memory list")
	}
}